Two-dimensional memory organization

Two-dimensional memory organization

 

 

Two-dimensional memory organization

 

Meaning of Two-dimensional memory organization

Two-dimensional memory organization memory organization in which the arrangement on a single chip reflects the logical arrangement of memory. In the most straightforward case, each address is presented at once in its entirety and decoded by a single decoder. However, to reduce the number of pins required for addressing, the address may be split into two parts that are then sent in sequence on the same lines. Then during the row access strobe, one part is used to select a “row” of the memory, and during the column access strobe the other part is used to select a “column” of the selected “row.” The “row” output may be held in a buffer and the “column” access then applied to the contents of the buffer.

 

Source: http://ee.sharif.edu/~lcsl/useful/Electrical%20Engineering%20Dictionary.pdf

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Author of the text: Ed. P.A. Laplante Boca Raton: CRC Press LLC, 2000

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Two-dimensional memory organization

 

Two-dimensional memory organization

 

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Two-dimensional memory organization

 

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Two-dimensional memory organization